Robust power management in the IBM z13

نویسندگان

Tobias Webel

P. M. Lobo

Ramon Bertran Monfort

Gerard Salem

Malcolm Allen-Ware

Richard F. Rizzolo

Sean M. Carey

Thomas Strach

Alper Buyuktosunoglu

Charles Lefurgy

Pradip Bose

Ricardo Nigaglioni

Timothy J. Slegel

Michael S. Floyd

Brian W. Curran

چکیده

in the IBM z13 T. Webel P. M. Lobo R. Bertran G. M. Salem M. Allen-Ware R. Rizzolo S. M. Carey T. Strach A. Buyuktosunoglu C. Lefurgy P. Bose R. Nigaglioni T. Slegel M. S. Floyd B. W. Curran The power management strategy adopted for the IBM z13i processor chip (referred to as the CP or Central Processor chip) is guided by three basic principles: (a) controlling the peak power consumption by setting a realistic limit on the so-called thermal design power or thermal design point (TDP) driven by customer workloads and maximum-power stress microbenchmarks; (b) reduction of the voltage margin by using a novel dynamic guard-banding technique; and (c) the creation of a rich new set of fine-grained, time-synchronized sensors that track performance, power, temperature, and power management behavior for a running machine. A prime requirement of the power management architecture is that the efficient control mechanisms be designed in such a manner that the high standards of IBM z Systemsi application performance and reliability be maintained without any compromise. In this paper, we describe the key features constituting the z13 CP robust power management architecture and design that meet the stipulated objectives.

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